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開發ADC應用就像在操作示波器一樣容易
2016/07/27
Keyword: YouTube720x480畫質Full HD畫質
當您在使用Sigma-Delta ADC IC的時候是否曾經發生下列的狀況:
1. 在debug的過程中曾經懷疑感測器的輸出信號有問題,但卻又無法即時明確的指出信號的問題所在?
2. 調整ADC的放大倍率、參考電壓位準以及取樣速度的時候,ADC的輸出數值範圍也會跟著改變,一不小心就會讓數值超過ADC的飽和上下限。

TR8124是tenx推出的一款24-bit Sigma-delta ADC IC,也同時推出其專屬的ADC開發評估工具(ENOB tester)。
這套開發工具提供了一個將ADC輸出數值即時轉換成波形的功能,當您將感測器連接到開發工具之後,透過這個功能您
不但可以直接看到ADC輸出信號的波形,在調整ADC的各項參數的時候也能立即觀看到ADC輸出所產生的位準變化,大
幅簡化ADC應用在開發前期的複雜性。
 

相關的展示影片請參考下方的連結:
YouTube

720x480畫質

Full HD畫質
BLOCK DIAGRAM




FEATURES
1. Design for front-end signal processing of sensor:
  . Embedded 24-bit Sigma-Delta A/D Converter.
  . AVDD’s driving capability is about 10mA.
  . Two clock source options: external X’TAL or internal RC OSC.
  . I2C interface.
2. Operation range:
  . Supply voltage range: 2.4 to 3.6V.
  . Operation current consumption:
    (1) Normal operation: 1.5 mA (ADC clock frequency is 81.92 kHz and conversion rate is 10 Hz).
    (2) Low power operation: <1 mA (VBG: external in and <1.2V or setting tune-I registers, IBAS[1:0] ).
3. 24-bit Sigma-Delta ADC:
  . Embedded 3 differential input channels.
  . Built-in PGIA, with gain options : 1X, 2X, 4X, 8X, 16X, 32X, 64X, 128X.
  . PD-PGIA mechanism, with gain options: 1X, 2X, 4X.
  . Conversion rate is 10 SPS when ADC clock frequency is 81.92 kHz. It could be 
     tuned by frequency-divider registers, OSCD[2:0]. (50 Hz/60 Hz rejection 
     function works while ADC clock frequency is 81.92 kHz).
  . RMS noise is 140 nV at 10 SPS conversion rate, PGA gain option is 128X.
  . ENOB is 17.5 bits. (Gain=128X, REFP=1.65V, VDDO=3.3V, OSR=8192)
  . Tunable internal bias current : Ibias, Iabias, Ibfbias.
  . Tunable Over Sampling Rate (OSR) : 1024, 2048, 4096 and 8192.
4. Built-in LDO (ENBGR=1) for AVDD and DVDD out:
  . AVDD out is 2.4V/2.6V/2.9V.
  . DVDD out is 2.2V/2.4V/2.6V.
5. Temperature sensor precision ±3°C (after calibration).

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