FEATURES1. Standard 8051 Instruction set, fast machine cycle
. Executes instructions six times faster than the traditional 8051.
2. 16K Bytes Flash Program Memory
. Support “In Circuit Programming” (ICP) or “In System Programming” (ISP) for the Flash code
. Byte Write “In Application Programming” (IAP) mode is convenient as Data EEPROM access
. Code Protection Capability
3. Total 768 Bytes SRAM (IRAM + XRAM)
. 256 Bytes IRAM in the 8051 internal data memory area
. 512 Bytes XRAM in the 8051 external data memory area (accessed by MOVX Instruction)
4. Three System Clock type Selections
. Fast clock from Internal RC (3.75MHz @VDD=3V)
. Slow clock from 32768Hz Crystal
. Slow clock from RFC
. System Clock can be divided by 1/2/4/8/16/32/64/128 option
. System Clock output pin (TCO) for EL / IR application
5. 8051 Standard Timer – Timer0 / 1 / 2
. 16-bit Timer0, also supports RFC clock input counting
. 16-bit Timer1, also supports T1O / T1B clock output for Buzzer / IR application
. 16-bit Timer2, also supports T2O clock output for Buzzer / IR application
6. 23-bit Timer3 used for Real Time 32768Hz Crystal counting
. ± 0.5 ppm ~ 61 ppm interrupt rate adjustable
. MSB 8-bit overflow auto-reload
. 0.25 sec, 0.5 sec, 1.0 sec or overflow Interrupt
7. 14-Channel Touch Key (F2261 only)
. 1~4 Key H/W Auto Scan Mode (ATK), Sensitivity Adjustable for each Key
. Interrupt / Wake-up CPU while Key Pressed
8. 8051 Standard UART
. One Wire UART option can be used for ISP or other application
9. SPI Interface
. Master or Slave mode selectable
. Programmable transmit bit rate
. Serial clock phase and polarity options
. MSB-first or LSB-first selectable
10. 11 Sources, 4-level priority Interrupt
. Timer0 / Timer1 / Timer2 / Timer3 Interrupt
. INT0 / INT1 Falling-Edge / Low-Level Interrupt
. Port1 Pin Change Interrupt
. UART TX/RX Interrupt
. P2.7 (INT2) Interrupt
. Touch Key Interrupt
. SPI Interrupt
11. Pin Interrupt can Wake up CPU from Power-Down (Stop) mode
. P3.2 / P3.3 (INT0 / INT1) Interrupt & Wake-up
. P2.7 (INT2) Interrupt & Wake-up
. Each Port1 pin can be defined as Interrupt & Wake-up pin (by pin change)
12. Max. 32 Programmable I/O pins
. CMOS Output
. Pseudo-Open-Drain, or Open-Drain Output
. Schmitt Trigger Input
. Pin Pull-up can be Enabled or Disabled
13. Resistance to Frequency Converter (RFC)
. RFC clock divided by 1/4/16/64 signal can be assigned as Timer0 event count input
. RFC clock can be used as System clock source
14. LCD Controller / Driver
. 1/3 ~ 1/10 Duty
. Max. 10 COM x 43 SEG
. LCD Bias Regulator Output (VL1) = 1.0V ~ 1.5V adjustable (16 steps)
. 1/3 or 1/4 LCD Bias, VL2 / VL3 / VL4 is Voltage Pump by VL1
. Frame Rate: 40~90Hz
15. LED Controller / Driver
. 1/3 ~ 1/6 Duty
. Max. 6 COM x 30 SEG
. 40 mA High Sink COM, Active Low
. Active High or Active Low Segment output
16. BandGap Voltage Reference for Low Battery Detection (LBD)
. Detect VBAT voltage level from 2.5V to 3.0V
17. Built-in tiny current LDO Regulator for chip internal power supply (VDD)
. VDD voltage level can be set from 1.2V to 1.8V in different mode
18. Watch Dog Timer based on System Clock
. Running in Fast / Slow Mode, Stop counting in Idle / Stop Mode
. 32K or 64K counts overflow Reset
19. 5 types Reset
. Power on Reset
. Selectable External Pin Reset
. Selectable Watch Dog Reset
. Software Command Reset
. Selectable Battery Low Voltage Reset (when VBAT<1.6V)
20. 4 Power Operation Modes
. Fast / Slow / Idle / Stop Mode
21. On-chip Debug / ICE interface
. Use P1.2 / P1.3 pin
. Share with ICP programming pin
22. Operating Voltage and Current
. VBAT=2.0V~4.2V
. 0.6uA LCD Current @VBAT=3V
. 0.1uA LVR Current @VBAT=3V
. 0.7uA 32K Crystal and System Clock Current @VDD=1.5V
. 0.5uA Touch Key Current @VBAT=3V
. Total 1.9uA Idle mode Current with LCD on, LVR on and TK scan @VBAT=3V, VDD=1.5V
23. Operating Temperature Range
. –40°C ~ +85°C
24. 64 / 80-pin LQFP Package